BIST for ring-address SRAM-type FIFOs
A.J. van de Goor, I. Schanstra, Y. Zorian · 2002
Testing FIFOs involves testing the embedded memory cell array, the addressing mechanisms, and the FIFO functionality logic (such as Empty and Full flags); each with their specific fault models. A test algorithm for the popular ring-address SRAM-type FIFOs has been published [Go94]; it consists of 36 steps and has a test length of 2n/sup 2/+10n+12+2/spl middot/Del (where n is the number of cells in the FIFO, and Del a delay time), while not all coupling faults are detectable due to the addressing restrictions of the FIFO. This paper presents a new test algorithm based on BIST which consists of 25 steps, reduces the test length to 21n+13+2/spl middot/Del, and allows for full fault coverage. It has been implemented as part of a macro-cell generator for FIFOs at AT&T Microelectronics. The paper describes the test algorithm, the BIST hardware, and the chip area overhead.>