Prototyping of a 5 GHz WLAN Reconfigurable System-on-Chip
Spyridon Blionas, Κωνσταντίνος Μασσέλος, Chrissavgi Dre, Christos Drosos, Fragkiskos Ieromnimon, D.E. Metafas, Thanasis Pagonis, Aristodemos Pnevmatikakis, Anna Tatsaki, Theodor Trimis, Adamandios Vontzalidis · IEICE Transactions on Information and Systems · 2003
SUMMARY In this paper the development of the prototyping platform of a partly reconfigurable System-on-Chip (SoC) for wireless LANs, is described. It is designed to realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The current version of the system includes Mobile Terminal and AP functionality only for indoor use. Future firmware versions (configurations for its reconfigurable part) will upgrade system’s functionality to allow its operation in outdoor environments and in wireless point-to-point links. The target System-on-Chip implementation platform will include instruction set processor cores, ASIC blocks and embedded reconfigurable blocks to achieve an optimal balance between implementation efficiency (area, power, performance) and flexibility. The system’s prototype is developed on the ARM integrator platform and all firmware versions