Stafan algorithms for MOS circuits
J. Villoldo, Rahul Agrawal, Vishwani D. Agrawal · 2002
Novel models and algorithms for MOS transmission gates, buses and functional memories for use in statistical fault analysis (Stafan) are described. A bus is modeled as a multiple input multiplexer with feedback to account for its memory state. A CMOS transmission gate, modeled as a unidirectional device, always feeds into a bus that processes the high impedance state. Novel algorithms are devised to compute input observabilities of functional memory blocks. A novel implementation of Stafan algorithms is described for the MARS hardware accelerator environment. MARs is run in the true-value simulation mode and sends signal changes for all lines through a Unix pipe to the Stafan process running on a SUN workstation. The Stafan process computes controllabilities, observabilities, detection probabilities, and fault coverage. MARS and Stafan thus run as a pipeline. Results on several CMOS circuits are obtained and compared with those obtained from a concurrent fault simulator.>