Design and FPGA implementation of digit-serial FIR filters
Javier Valls, M.M. Peiro, Trini Sansaloni, Eduardo Boemo · 2002
In this paper the design of a family of digit-serial 8th-order FIR filters with programmable coefficients is presented. Both input data and coefficient size are 8 bits, but every filter of the family allows the computation with full precision of the intermediate data. The output data is truncated to 8 bits. The design of both, the digit-serial multiple precision multiply-and-accumulate and the digit-serial multiple-to-single precision converter, is detailed. All filters were implemented using an ALTERA FPGA being useful in applications with sample rate range from 5 to 22 MHz.