A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip
Kwanho Kim, Joo-Young Kim, Seung‐Jin Lee, Minsu Kim, Hoi‐Jun Yoo · 2008
This paper presents a 211 GOPS/W real-time object recognition processor with network-on-chip (NoC). The chip integrates 8 linearly connected SIMD clusters with 8 4-way VLIW processing elements (PEs) per cluster. The SIMD/MIMD dual-mode object recognition processor exploits both data-level and object-level parallelism based on the NoC configuration. The 8-way SIMD PE cluster is optimized for data-intensive object recognition tasks. Packet-based power management scheme is employed for low power consumption. The proposed processor takes 36mm2in 0.13μm CMOS process and achieves a peak performance of 96GOPS at 200MHz with 392mW power consumption.