A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10−19
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto · 2011
We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operation. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 384 sets of unique 128-bit fingerprints from 12 chips, which were evaluated in this paper. The fail rate of the ID was found to be 4.45 × 10-19at a nominal supply voltage of 1.2 V and at room temperature. This scheme can be implemented for existing SRAMs through minor modifications. It has high speed, and is implemented in a very small area overhead.