Formal Verification of System Level Designs: A GSM Vocoder Case Study
Ghiath Al Sammane, Otmane Aı̈t Mohamed · 2007
System-level design of embedded systems is essential to enhance designer productivity. Several design methodologies has been emerged using languages such as SystemC or SpecC that addresses the industry's need for a fast time-to-market. The higher abstraction level offered by these new methodologies is a challenge to rigorous, formal verification. This paper describes the formal verification of designs written in SpecC at the specification level. The method is illustrated on a high level description of the GSM Vocoder: a voice encoder decoder based on the European GSM standard. We define a set of properties P that the GSM Vocoder should satisfy. Essentially, P describes the temporal specification of the Vocoder, including properties about: timing, concurrency, states transitions and communication.