A 1-micron VLSI implementation and design of a parallel Hough transformer
T. Mostafavi, Sanjay Vishin · 2003
A VLSI chip based on a parallel version of the Hough transform has been designed and implemented in 1- mu m CMOS. The chip accepts the incoming pixels serially and transforms it into a different parameter space while the expected feature is matched against the incoming pixels. A set of about 86 chips like this will be used to extract the features from a 256*256-pixel grey image. The parallel architecture and the simple operations on each pixel make it suitable for VLSI. Test vectors for the entire 1/4-million-transistor chip have been determined.>