An experimental chip to evaluate test techniques: chip and experiment design
P. Franco, W.D. Farwell, Robert L. Stokes, Edward J. McCluskey · 2002
An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25 k gate CMOS Test Chip has been designed, manufactured (5491 devices),and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.