Residue arithmetic techniques for hardware reduction in pseudo-random sequence correlators
Christopher T. Clarke, Thambipillai Srikanthan · 2005
The use of correlators to detect pseudo random number sequences is widespread, and forms the basis of pervasive technologies such as GPS. The correlation function is subject to a trade-off between hardware cost and speed. In this paper we present a residue arithmetic based technique that can create a pseudo random number sequence correlator that has both low hardware cost and high speed.