Profile-based Optimization of Power Performance by using Dynamic Voltage Scaling on a PC cluster
Yoshihiko Hotta, Mitsuhisa Sato, Hideaki Kimura, Satoshi Matsuoka, Satoshi Matsuoka, Taisuke Boku, Daisuke Takahashi · 2006
Currently, several of the high performance processors used in a PC cluster have a DVFS (Dynamic Voltage and Frequency Scaling) architecture that can dynamically scale processor voltage and frequency. Adaptive scheduling of the voltage and frequency enables us to reduce power dissipation without a performance slowdown during communication and memory access. In this paper, we propose a method of profiled-based power-performance optimization by DVFS scheduling in a high-performance PC cluster. We divide the program execution into several regions and select the best gear for power efficiency. Selecting the best gear is not straightforward since the overhead of DVFS transition is not free. We propose an optimization algorithm to select a gear using the execution and power profile by taking the transition overhead into account. We have built and designed a power-profiling system, PowerWatch. With this system we examined the effectiveness of our optimization algorithm on two types of power-scalable clusters (Crusoe and Turion). According to the results of benchmark tests, we achieved almost 40 % reduction in terms of EDP (energydelay product) without performance impact (less than 5%) compared to results using the standard clock frequency. 1