Crossbars with Minimally-Sized Crosspoint Buffers
Nikos Chrysos, Manolis G. H. Katevenis · 2007
Buffered crossbars are emerging as the architecture that will replace the bufferless core currently used in high-speed routers and switching fabrics. Their main drawback is the cost of N2crosspoint buffers, which must be implemented inside the crossbar chip. Using traditional credit-based backpressure, each such buffer may need to hold several tens of cells due to the non-negligible linecard-crossbar round-time. In this paper we present credit prediction, a method that renders the requirements on crosspoint buffer space independent of the linecard-crossbar round-trip time. Credit prediction uses a central scheduler, but scheduling operations at inputs and at outputs are pipelined and run in parallel, just as in traditional (distributed) buffered crossbars. In terms of performance, our scheme performs identically with traditional buffered crossbars when the linecard-fabric round-trip time is zero, while it achieves considerable buffer savings as this round-trip time increases. Effectively, with our method we can build effective buffered crossbars, using just one or two cells buffer per crosspoint.