HiBRIC-MEM, a memory controller for PowerPC based systems
Mario Porrmann, Jörg Landmann, Karl Michael Marks, Ulrich Rückert · 2002
This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Interface Controller) provides control for up to two PowerPC processors. A look-ahead mechanism, called stream cache, is used to reduce the effective memory latency and a 12-bit error correction code is available for optimal system security. Initial silicon was produced in a 0.7 /spl mu/m, three metal layer Motorola technology and has a die size of 12.1/spl times/12.1 mm/sup 2/. HiBRIC-MEM is used, for example, in a commercially available parallel computer.