An efficient architecture for loop based data preloading
William Y. Chen, Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, James E. Sicolo · ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter · 1992
Cache prefetching with the assistance of an optimizing compiler is an eflectiue means of reducing the penalty of long memory access time beyond the primary cache. However, cache prefetching can cause cache pollution and its benefit can be unpredictable.A new architectural support for preloading, the preload buffer, is proposed in this paper.Unlike previously proposed methods of non-binding cache loads, the preload is a binding access to the memory system.The preload buffer is simple in design and predictable in performance.Simple interleaving permits accesses to the preload bufler to be free of bank conflicts.Trace driven system simulation is used to show that the performance achieved with preloading hides memory latency better than either no prefetching or cache prefetching.In addition, both bus tmfic mte and cache miss rate are reduced.