Low power and cost effective scaling engine with locking frame rate for display controllers
Chung-Hsun Huang, Chao‐Yang Chang · IEEE Transactions on Consumer Electronics · 2011
Embedded memory typically requires significant silicon chip area, and in the case of display controller chip designs with a locking frame rate, it entails high power consumption. In this paper, we introduce a low-power cost-effective scaling engine with locking frame rate, with reduced memory capacity requirements. Using our proposed H-V scaling direction-interchangeable architecture, the scaling engine can dynamically adjust the data processing flow for reduced memory usage and lower power consumption. Evaluating the cost and power consumption, and in comparison with two conventional scaling engines, our proposed design reduces embedded memory requirements by 76% and 10% in the two cases, and has 99% and 18% lower power consumption, respectively.