Reducing Complexity of FIR Filter Implementations for Low Power Applications
Linda S. DeBrunner · 2018 52nd Asilomar Conference on Signals, Systems, and Computers · 2007
One way to achieve low power consumption in the implementation of DSP algorithms is to develop low complexity hardware designs. By reducing the number and size of the multiplications and additions, we can realize significant reduction in the power consumption of the hardware. This paper explores a combination of techniques to develop low complexity, low power implementations for FIR filters. We use a multiplierless design with quantization techniques to limit the number of bits used in computations. The benefit of this approach is discussed with respect to FPGA and general VLSI implementations.