Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 2007
This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints