Implementation of Linear Algebra Algorithms in FPGA-based Rational Fraction Arithmetic Units
Oleg Maslennikow, Piotr Ratuszniak, Anatoli Sergyienko · 2007
In this paper, two fixed size processor array architectures, which are destined for realization of several linear algebra algorithms, are proposed. In order to implementation of these architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed, which is adapted to realization in the Xilinx reconfigurable platforms Virtex II or Virtex 4 families. It allows to reduce the hardware complexity of the new AU up to 4,5 times in comparison with similar AUs operating with float-point numbers, without decreasing of AU performance and increasing round off errors.