Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus
Toshimasa Namekawa, Satoru Miyano, Ryota Fukuda, Ryousuke HAGA, Osamu Wada, Hironori Banba, Susumu Takeda, K. Suda, K. Mimoto, Sakuya Yamaguchi, Tetsui Ohkubo, Hiroshi Takato, Kenji Numata · IEEE Journal of Solid-State Circuits · 2000
A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is presented. This redundancy reduces the area required for spare cells from 6 to 1.6% of the area required for normal cells and improves chip yield from 50 to 80%. In addition, it provides a high-speed data path. An embedded DRAM macro adopting the redundancy achieves 200-MHz operation and provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-/spl mu/m technology.