VLSI implementation of a low-power antilogarithmic converter
Khalid H. Abed, R. Siferd · IEEE Transactions on Computers · 2003
This paper presents a VLSI implementation of a unique 32-bit antilogarithmic converter, which generates data for some digital-signal-processing (DSP) applications. Novel antilogarithm correcting algorithms are developed and implemented with low-power and hardware-efficient correcting circuits. The VLSI implementations of these algorithms are much smaller than other hardware intensive algorithms found in the literature. The converter is implemented using 0.6 /spl mu/m CMOS technology, and its combinational logic implementation requires 1500/spl lambda//spl times/2800/spl lambda/ of chip area. The 32-bit antilogarithmic converter computes the antilogarithm in a single clock cycle and runs at 100 MHz and consumes 81 mW.