Design And Verification Based On Assertions: Some Statistics
Joaquín Cortez, Deni Torres-Román · 2005
Usually, the assertion based verification (ABV) is used for the formal verification of digital design. In this work, we show that it can be used also for the code implementation in a hardware description language (HDL), saving time and improving the whole design process. Property specification language (PSL) was used for the written of assertions for a specific circuit. Finally, a set of properties for finite states machines (FSM) was established.