High-speed error correcting code LSI with throughput of 5 to 48 Gbps
Yuuichi Hamasuna, M. Hata, Ichi Takumi · 2003
We proved that the hardware implementation of the proposed code and the new packet synchronization system was effectively realized by using a unique circuit configuration. A three-dimensional size-five coder and decoding-synchronization system was implemented on FPGA. The developed FPGA was applied to a high-speed MPEG communication device, which can transmit a movie signal of 20 Mbps.