A BiCMOS 50 MHz cache controller for a superscalar microprocessor
Bharat S. Joshi, R.K. Anand, Christoph Berg, J. Cruz-Rios, A. Krishnamurthi, Nancy Nettleton, S. Nguyen, J. Reaves, J. Reed, A. Rogers, Stefan Rusu, C. Tucker, C. Wang, M. Wong, D. Yee, J. Chang · 2003
A description is given of a BiCMOS 50-MHz, 2.2 M-transistor cache controller (CC) chip which supports up to 2 MB of direct-mapped secondary cache for a superscalar microprocessor chip (PU) and interfaces with two multiprocessor (MP) buses. One is the MBus, a circuit-switched MP system bus operating at TTL (transistor-transistor logic) levels. The other is the XBus, a local packet-switched bus operating at either TTL or Gunning-transceiver logic (GTL) levels. In XBus mode, the CC connects to MP buses through buswatcher chips, up to four of which can be connected to the CC to support 4 MP buses. With XBus interface, the CC can support customized MP buses.>