Pseudo vector processor for high-speed list vector computation with hiding memory access latency
Hiroshi Nakamura, Toshio Wakabayashi, K. Nakazawa, Taisuke Boku, Hiroshi Wada, Yasuhiro Inagami · 2002
We present two scalar processors called PVP-SWPC and PVP-SWSW for high-speed list vector processing. Memory access latency should be tolerated for this objective. PVP-SWPC tolerates the latency by introducing slide-windowed floating-point registers and prefetch-to-cache instruction. PVP-SWSW tolerates the latency by introducing slide-windowed general and floating-point registers. Owing to the slide-window structure, both processors can utilize more registers in keeping upward compatibility with existing scalar architecture. The evaluation shows that these processors successfully hide memory latency and realize fast list vector processing.>