Extension of t oundary-Scan Architecture an for More Effective Testing and Self-Testing of Interconnections.
Adam Kristof · 1997
The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which however do not violate the JTAG/IEEEI149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test per$ormunce. Summary The proposed idea of BIST enables easy and reliable testing of interconnections. A BIST mechanism, normally reserved for testing cores of ICs, in this case is used for testing exterior of ICs, a set of interconnections. The proposed BIST, let us call it INETBIST, is intended to be a part of the Boundary-Scan Architecture, [ 11. It is assumed that the Split Boundary-Scan Registers, [2], are implemented. To achieve the ootimal test generator the Output B-S Registers of particular ICs are arranged into a single chain using standard TDI and TDO terminals, see Fig. 1.