VLSI implementation of a selective median filter
Chun-Te Chen, Liang‐Gee Chen, Jue-Hsuan Hsiao · IEEE Transactions on Consumer Electronics · 1996
The VLSI implementation of a selective median filter for real-time applications is presented. The proposed design is based on a novel bit-level running algorithm with a modular and parallel structure. A chip designed by the cell-based style is demonstrated to show the hardware realization. The performance of the proposed design is also presented.