Miss reduction in embedded processors through dynamic, power-friendly cache design
Garo Bournoutian, Alex Orailoğlu · 2008
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional methods for addressing performance and determinism become inadequate. This paper explores a new data cache design for use in modern high-performance em-bedded processors that will dynamically improve execution time, power efficiency, and determinism within the system. The simulation results show significant improvement in cache miss ratios and reduction in power consumption of approxi-mately 30 % and 15%, respectively.