Pipelined 16k Buffer RAM with 300MHz Operating Frequency
Doris Schmitt‐Landsiedel, Brooke Hoppe, G. Neuendorf, M. Wurm, Josef Winnerl · 1989
A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.