Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution
Pramod Kumar Meher · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2006
Novel one- and two-dimensional systolic structures are designed for computation of circular convolution using distributed arithmetic (DA). The proposed structures involve significantly less memory and less area-delay complexity compared with the existing DA-based structures for circular convolution. Besides, it is shown that the proposed systolic designs for circular convolution can be used for computation of linear convolution as well