Parametric Bridging Fault Characterieation for the Fault Simulation of Library-Based ICs
Marcello Dalpasso, Michele Favalli, Piero Olivo, B. Riccò · 2005
This paper presents a new approach to the fault simulation of parametric bridgings in CMOS ICs synthesized by means of libraries of macro-gates. The method is based on a fast but accurate preliminary characterization of any macro-gate for each input set. Such a characterization provides all information to determine, during the actual fault simulation, the maximum value of resistance for any considered bridging that makes the fault observable at a circuit primary output. This library characterization is very general, and can be used with any fa.ult simulation technique. Results on several benchmarks show that this approach allows the fault simulation of internal parametric bridging faults in a time comparable to that of the classical line stuck-ats.