VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
Jinhyun CHO, Doowon Lee, Sang-Yong Yoon, Sang‐Gyu Park, Soo‐Ik Chae · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2009
In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30fps at 80MHz. We implemented the decoder with a one-poly eight-metal 0.13μm CMOS process, which contains about 261, 900 logic gates and on-chip memories of 13.9KB SRAM and 13.1KB ROM and occupies an area of about 5.1mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.