High-speed forward error correction IP blocks for system-on-chip design
Anh Dinh, R.J. Bolton · 2003
High-speed forward error correction IP (intellectual property) blocks suitable for system-on-chip were designed for a wireless communications transceiver. Synthesizable HDL (hardware description language) code was written for the blocks including a differential encoder/decoder, a Reed-Solomon encoder/decoder and a convolutional interleaver/deinterleaver. The code was compiled, tested and verified for timing and function in both FPGA and 0.18 /spl mu/m CMOS.