The first MAJC microprocessor: a dual CPU system-on-a-chip
A. Kowalczyk, Victor Adler, C. Amir, F. Chiu, Choon Ping Chng, Walter Lange, Yuefei Ge, Subhendra Ghosh, Tan Hoang, Baoqing Huang, Shashi Kant, Y.S. Kao, Cong Khieu, Suresh Kumar, Lan Lee, A. Liebermensch, Xin Liu, N.G. Malur, Ambrozy Martin, Hiep Ngo · IEEE Journal of Solid-State Circuits · 2001
The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data (SIMD), and chip multiprocessing. The chip integrates two processors, a memory controller, two high-speed parallel I/O interfaces, and a PCI controller. The chip, fabricated in a 0.22-/spl mu/m CMOS process with six layers of copper interconnect, contains 13 million transistors and operates at 500 MHz. It is packaged in a 624-pin ceramic column grid array using flip-chip assembly technology.