Floating-point to fixed-point compilation and embedded architectural support
Tor M. Aamodt · Library and Archives Canada (Government of Canada) · 2001
Recently, software utilities for automating the translation of floating-point signal-processing applications written in ANSI C into fixed-point versions have been presented. This dissertation investigates a novel fixed-point instruction-set operation, Fractional Multiplication with internal Left Shift (FMLS), and an associated translation algorithm, Intermediate-Result-Profiling based Shift Absorption (IRP-SA), that combine to enhance fixed-point rounding-noise and runtime performance when supported by a utility that directly targets the instruction set. A significant feature of FMLS is that it is well suited to the latest generation of embedded processors that maintain relatively homogeneous register architectures. FMLS may improve the rounding-noise performance of fractional multiplicat...