Influence of Write-Buffer on the Performance of Hierarchical Memory Systems
A. Sra, Anmol V. Singh · 2005
This study reports on the influence of a Write-buffer on overall performance of a hierarchical memory system where the Writebuffer resides between Cache and main memory. Overall performance here is seen as a function of total number of cycles taken by the simulated system to finish a given! task. In bus based systems where write-buffer is located at the helm of bottleneck known as bus contention, write accesses to main memory are buffered so that the processor can begin a new cycle without waiting for the write cycle to complete. Reads to system memory cannot be buffered because the processor has to get read data before proceeding further. Handling Reads while buffering Writes can be done using more than one protocol. We studied three different protocols and selected one of them for most of the simulations. Writethru caches were used in simulation because they generate more bus traffic (Writes) compared to writeback caches.