High performance reconfigurable floating-point arithmetic modules
G.H.A. Aty, I.S. Ashour, M. Mones · 2005
This paper presents the design, optimization and implementation of floating- point arithmetic modules on FPGA to be used in DSP appkications. These modules are floating-point multiplier, floating-point adderhbtractor, floating-point complex multiplier, floating-point complex adder/subtractor and floating-point multiplier-accumulator (MAC). The simulation and the Synthesis results for these modules are provided. All the modules presented in this paper support creation of custom floating-point format, making them suitable for different requirements of signal formats in digital signal processing. Fast Fourier Transform (FF'), which is one of the most utilized operations in digital signal processing and communications, is used as an application example. A butterfly unit that can be used in Fast Fourier Transform (FFT) is designed using these optimized arithmetic modules. A pipelined FFT is presented using the designed butterfly unit. The design targeted Xilinx (Virtex 11) FPGA series.