A unified systolic array design for kernel functions of video compression
Poi Lin Tai, Chii Tung Liu, Jia Shung Wang · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2001
In video compression, some kernel functions such as block matching, discrete wavelet transform, vector quantization, etc., are of prime essential, but with a large amount of computation. Recently, many systolic array architectures have been designated for performing each of those functions in real time. In fact, many kernel functions contain the similar computational procedure. If we dissect these functions into the basic matrix-vector product forms, a unified design for them becomes feasible. In this brief, by carefully extracting the common computation component, a unified one-dimensional systolic array design that can perform at least the above three functions is presented. In this design, the input data is serial-in to save the amount of pins required, and the data flow are carefully arranged to simplify the interconnection between computation components. When 64 registers are in the on-chip memory, our design can perform three typical functions: (1) the full-search block matching with block size 16/spl times/16 and the search range (-8,7); (2) the 2-D Harr transform with block size 8/spl times/8; and (3) the vector quantization with input vector size 4/spl times/4 and codebook size 256. Since the unified architecture reduces hardware costs, and has a regular hardware structure, it is suited for VLSI implementation for video/image compression applications that require all the functions.