Parallel digital image restoration using adaptive VLSI neural chips
J.-C. Lee, B.J. Sheu · 2002
Real-time digital image restoration using massively parallel Hopfield neural chips is presented. An efficient mixed-signal VLSI design with analog circuitry to perform neural computation and digital circuitry to process multiple-bit pixel information greatly reduces the network size. Analog programmable synapse cells of 8 bit accuracy are dynamically refreshed. The gain-adjustable neurons enable electronic annealing to quickly reach global minimum in energy function. A prototype 25-neuron chip occupies a silicon area of 4.6*6.8 mm/sup 2/ in MOSIS 2- mu m CMOS process has been designed and tested. The speedup factor for each chip is 90 compared to the Sun-3 workstation. An 100-neuron image-restoration chip is achievable in the industrial-level 1- mu m technologies.>