Integrating scan into hierarchical synthesis methodologies
J. Beausang, C. Ellingham, M. Robinson · 2002
This paper presents new strategies for integrating scan DFT (design for test) techniques into hierarchical synthesis methodologies to meet the challenges of system-on-a-chip ICs (integrated circuits). It describes what can be done before, during and after synthesis to reduce design time, and presents results that show the effects of select approaches.