The design and implementation of the Arithmetic Cube II, a VLSI signal processing system
Robert Michael Owens, Thomas P. Kelliher, M.J. Irwin, Mohan Vishwanath, R.S. Bajwa, W.-L. Yang · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993
The Arithmetic Cube II, a high-performance signal processing system designed and built at Penn State University, is described. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008-point complex-in complex-out discrete Fourier transform (DFT) in 3.54 ms. This high performance rate is achieved using very modest technology (2- mu CMOS). An overview of the small-n algorithms is provided. The architectural design and implementation of the system and the transform development environment are described, and results of operating the system are reported.>