FIR filter mapping and performance analysis on MorphoSys
H. Diab, E. Abdennour, Fadi Kurdahi · 2002
This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) from UCI. A mapping of the FIR filter algorithm onto this hardware is proposed. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the FIR execution on the M1 system. An example (8-tap FIR filter on an 8/spl times/8 RC array M1) was run, to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operation.