An efficient BIST method for testing of embedded SRAMs
M.H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie · 2002
We have developed an algorithm to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This is achieved by writing a routine called BIST Program which only uses the existing ROM and creates no additional hardware overhead. BIST Program implements the "length 9N" test algorithm. The proposed test algorithm covers 100% of faults under the fault model plus a data retention test. A memory faults diagnostic capability is also provided by the BIST Program. This method can be implemented for embedded SRAM testing of all microprocessors, microcontrollers and DSPs. This test algorithm is experimented on 32 K SRAM of the Texas Instruments TMS320C548 DSP.