Modify the µCS-51 with Vector Instructions
Assem Badr, A. Fouda · 2012
Computer architects have always strived to increase the overall speed of processing for the CPUs. utilizing a reserved unused machine code "A5H", we can expands the tradition instruction set architecture (ISA) for the µCs-51 family, in this paper we introduce modification of internal architecture for the µCs-51 and their ISA to improve the overall µC performance, specifically we will introduce two innovated vector instructions for the µCs-51 family. The two vector instructions exploiting the data manipulation. The first instruction is to transfer a block of data from specific memory locations to any other memory locations simultaneously, while the other vector instruction is to obtain the minimum data byte value within a block of data bytes. Also we will supply the modified µC with pipeline technique for decreasing the total execution time. Such development improves the total performance of the µC including execution time, and storage ratio.