Memory-efficient and high-performance parallel-pipelined architectures for 5/3 forward and inverse discrete wavelet transform
Tze‐Yun Sung · 2007
In this paper, high-efficient lifting-based architectures for the 5/3 forward and inverse discrete wavelet transform (DWT) are proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The system delays of the proposed architectures are reduced. Filter coefficients of the biorthogonal 5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architectures, all multiplications are performed using less shifts and additions. The proposed parallelpipelined architectures are 100 % hardware utilization and ultra low-power. The architectures have regular structure, simple control flow, high throughput and high scalability. Thus, they are very suitable for new-generation image compression systems, such as JPEG-2000.