An optimal time expansion model based on combinational ATPG for RT level circuits
Tomoo Inoue, T. Hosokawa, Takahiro Mihara, Hideo Fujiwara · 2002
We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We performed experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scan while preserving almost 100% fault efficiency.