An integrated high-level test synthesis algorithm for built-in self-testable designs
Laurence Tianruo Yang, Jon C. Muzio · Symposium on Integrated Circuits and Systems Design · 2002
Describes a high-level test synthesis algorithm for operation scheduling and data path allocation. It generates highly self-testable data path design while maximizing the sharing of test registers, which means only a small number of registers is modified for BIST. The algorithm also produces design with high test concurrency, thereby decreasing test time. In the approach, module allocation is guided by a testability balance technique. Register allocation is achieved by an incremental sharing measurement which chooses allocation steps that result in large increases in the sharing degrees of registers. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.