Fault tolerant arbiters for synchronous multiple bus systems
Syed Masud Mahmud, S. Shetty, C.P. Karamatas, P. Gopalakrishna · 1991
An arbitration circuit for a multiple bus system was designed using M number of N-to-1 arbiters and one M-user B-server (M-to-B) arbiter, where M, N and B are the number of memory modules, processors and buses, respectively. A new design of an M-to-B arbiter was presented by S.M. Mahmud and M. Showkat-Ul-Alam (1990), but this arbiter does not work properly when one or more buses become faulty, and does not have the reconfigurable feature. The authors present the design of a reconfigurable M-to-B arbiter. The performance of the arbiter has been evaluated using simulation. The results show that the arbiters work as they are supposed to under different bus fault conditions.>