The hardware results of a 64×64 analog input array for a 3-dimensional neural network processor
T.A. Duong, Tedy Thomas, T. Daud, A. P. Thakoor, S. Suddarth · 2002
Algorithms for the solution of spatio-temporal recognition and classification problems are known to require intense image data computation. To develop a viable hardware solution for such a task, we have focused on the development of a 3D artificial neural network (3DANN). It consists of a set of low power analog chips packaged as a 3D "sugar cube" mated to an infrared imager to conform to highly parallel processing at very high speeds. The challenge of delivering highly parallel image data input (64/spl times/64 bytes of data in parallel every 250 nanoseconds) has been met by the design of an innovative chip architecture, termed the column loading input chip (CLIC). The CLIC replaces the imager on the cube and can be connected to an image frame grabber or a high-speed data formatter through the sugar cube motherboard. This scheme of 3DANN modification has been developed, which consists of a CLIC and a 3D neural processing module.