A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller
Deog‐Kyoon Jeong, David Alvra Wood, Garth A. Gibson, Susan J. Eggers, David A. Hodges, Randy Howard Katz, David A. Patterson · IEEE Journal of Solid-State Circuits · 1989
For pt.I see ibid., vol.24, no.6, p.1688-98 (1989). The authors describe a memory management unit and a cache controller (MMU/CC) for a 40-70-MIPS multiprocessor workstation. The MMU/CC implements a novel memory management scheme, in-cache address translation, which does not require a translation lookaside buffer. It also implements a snooping bus protocol to maintain data consistency across all caches in the system. The chip is implemented in a 1.6- mu m double-layer-metal CMOS technology and is being used in a multiprocessor workstation (SPUR) successfully executing a UNIX-like network-based operating system called Sprite as well as many applications, including LISP programs.>