A BIST scheme using microprogram ROM for large capacity memories
Hiroki Koike, Tsubasa Takeshima, M. Takada · 2002
A practical microprogram ROM BIST (built-in self-test) scheme suitable for LSI memories is proposed. This BIST can be used to install N-pattern and N/sup 2/-pattern test procedures, using BIST circuits with 12-word*10-b and 16-word*16-b ROMs, respectively. As a practical test procedure, a data retention test, in which BIST circuits with an 8-word*11-b ROM were used, was investigated. BIST circuit area overheads for the above three test patterns for 16-Mb DRAMs are less than 1%, 2%, and 1.5%, respectively. A testing method for the BIST circuits themselves, with no special BIST circuit overhead, is also proposed for more practical applications. The measured operational margin for a 16-Mb DRAM using the BIST showed a good agreement with that using an LSI tester.>